August 17-19, 2011 at Memorial Auditorium, Stanford University

Tutorials, August 17, 2011

Tutorial 1: Package-Scale Power Management, UC Berkeley

• Practical power gating and dynamic voltage/frequency scaling issues (AMD)
• Integrated Inductors with Magnetic Materials for On-Chip Power Conversion (Intel)
• Fully Integrated Switched-Capacitor DC-DC Conversion (UC Berkeley)

Tutorial 2: Open Compute Project, Facebook

The Open Compute Project: Building an Open Community Focused on Data Center Design For Web-Scale Computing

• Project motivation and high level system design, Amir Michael
• Open Compute Storage Design
• Server Board Design, Harry Li
• Efficient Power Distribution, Pierluigi Sart

Conference Day 1, August 18, 2011

Session 1: Many Core

• Cavium 32 core OCTEON II CN68xx, Richard Kessler, Cavium
• IBM Blue Gene/Q Compute chip, Ruud A. Haring, IBM
• The Highly-Efficient Architecture of Godson-T Many-Core Processor, Dongrui Fan, Hao Zhang, Da WangXiaochun Ye, Fenglong Song, Junchao Zhang,Lingjun Fan, ICT, Chinese Academy of Sciences

Session 2: Security

• Intel’s Digital Random Number Generator (DRNG), George Cox, Charles Dike and David J Johnston, Intel
• TILE-Gx ManyCore Processor: Acceleration Interfaces and Architecture, Carl Ramey, Tilera
• Building a 40 Gbps Next Gen. Virtualized Security Proc., Jeff Pangborn,Cavium

Keynote 1

• ARM Processor Evolution: Bringing High Performance to Mobile Devices, Simon Segars, VP, ARM

Session 3: Memory & FPGA

• Bandwidth Engine Serial Memory Chip Breaks 2 Billion Accesses/sec, Michael Miller, Mosys
• Hybrid Memory Cube (HMC), J. Thomas Pawlowski, Micron
• Xilinx Zynq Embedded Processing Platform, Sandeep Dutta, Vidya Rajagopolan, Brad Taylor, Ralph Wittig, Xilinx

Session 4: DSP

• XMOS Architecture: XS1 chips, David May, XMOS
• Worlds’ Fastest DSP Core: Breaking 100 GMAC/s Barrier, Chris Rowen,Tensilica

Session 5: Miscellaneous

• Rethinking Algorithms for Future Architectures: Communication-Avoiding Algorithms, James Demmel, UC Berkeley
• Electrons, Photons, Phonons, Wave, Bits, and Industrial Design: Microsoft Kinect Sensor, Dawson Yee, Scott McEldowney, Microsoft

Panel Discussion: The Ecosystem Wars: It’s Not Just About Architecture

Chair: Forest Baskett, NEA, Jim Turley, Silicon Insider, moderator, Nick Tredennick, PhD, IEEE Fellow,
Jim Ready, CEO MontaVista, founder Ready Systems, Cofounder Hunter & Ready, Robert Day, VP Marketing, LynuxWorks, Jim St. Leger, ECG Technology Marketing, Intel, John Heinlein, PhD, VP Marketing, ARM

Friday, August 19, 2011

Session 6: Networking

• Low Power High Density 10GBASE-T Ethernet Transceiver, Ramin Shirani, Ramin Farjadrad, Aquantia
• One Billion Packet per Second Frame Processing Pipeline, Mike Davies,Fulcrum
• Sereno: A 2nd-Generation Virtualized Network Interface Controller, Mike Galles and Shrijeet Mukherjee, Cisco

Session 7: Server

• SeaMicro SM10000-64 Server: Building Datacenter Servers Using Cell Phone Chips, Ashutosh Dhodapkar, Gary Lauterbach, Sean Lie, SeaMicro
• Poulson: An 8 Core 32 nm Next Generation Intel* Itanium* Processor, Stephen Undy, Intel
• T4: A Highly Threaded Server-on-a-Chip with Native Support for Heterogeneous Computing, Robert Golla, Paul Jordan, Oracle

Keynote 2

• Challenges of Building Personal Robots, Steve Cousins, Willow Garage

Session 8: Video

• 1TOPS/W Software Programmable Media Processor, David Moloney, Movidius
• Intel* Quick Sync Video Technology in the 2nd Generation Intel Core Processor Family, Hong Jiang, Intel

Session 9: Desktop CPUs

• 2^nd Generation Intel* Core* Processor Family: Intel Core i7, i5 and i3, Oded Lempel, Intel
• Power Management Architecture of the 2nd Generation Intel* Core* microarchitecture, formerly codenamed Sandy Bridge, Efraim Rotem, Alon Naveh, Doron Rajwan and Avinash Ananthakrishnan,Eli Weissmann, Intel
• AMD’s Llano Fusion APU, Denis Foley, Maurice Steinman, Alex Branover, Antonio Asaro, Ljubisa Bajic, Swamy Punyamurtula and Greg Smaus, AMD
• High Performance Power-Efficient x86-64 Server & Desktop Processors: using Bulldozer core, Sean White, AMD

Student Posters: on display during the Conference Breaks

• A Few Ways Can Take You a Long Way: Efficient and Highly Associative Caches with Scalable Partitioning for Many-Core CMPs, Daniel Sanchez, Christos Kozyrakis, Stanford
• VENICE: A Compact Vector Processor for FPGA Applications, Aaron Severance, Guy Lemieux,University of British Columbia
• The Utility of Fast Active Messags on Many-Core Chips, R. Curtis Harting, Vishal Parikh, William Dally, Stanford
• Efficient Fetch Mechanism by Employing Instruction Register, Mochamad Asri, Tokyo Institute of Technology
• Tessellation Operating System: Building a real-time, responsive, high-throughput client OS for many-core architectures, Juan Colmenares, Sarah Bird, Gage Eads, Steven Hofmeyr, Albert Kim, Rohit Poddar, Hilfi Alkaff, Krste Asanovic, John Kubiatowicz, UC Berkeley
• The Maven Vector-Thread Architecture, Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic, UC Berkeley